1. Field of the Invention
The present invention relates to a level shift circuit, and in particular to a level shift circuit with faster output level switching, and a method for the same.
2. Description of the Related Art
A level shift circuit is for use to convert a DC voltage level from low to high (such as from 5V to 12V or 23V, etc.), or from high to low (such as from 12V to 5V or 3V, etc.); a level shift circuit is often used in a power control circuit chip. FIG. 1A shows the basic structure of a conventional level shift circuit 10, which comprises two PMOS transistors M1 and M2, and two NMOS transistors M3 and M4. Assuming the function of the circuit is to convert the voltage level from 5V to 23V, the input IN in the shown circuit may thus be an operational voltage of 5V (the first operational voltage), and the voltage supplied from the voltage source VP2 may be 23V (the second operational voltage).
Referring to FIGS. 1A and 1B, the conventional level shift circuit operates as follows. At time T0, the initial state of the circuit, the input IN is at the low level of the first operational voltage (e.g., 0V), while the inverted input INB is at the high level of the first operational voltage (e.g., 5V). Because the inverted input INB is at the high level, the NMOS transistor M4 is ON, whereby the node B is grounded through NMOS transistor M4 and is at the low level of 0V. The voltage level of the node B is exactly the voltage level of the output OUT, which is thus also at the low level of 0V. Because the node B is low, the PMOS transistor M1 is ON, whereby the voltage VP2 reaches the node A through the PMOS transistor M1 so that the node A is at a high level equivalent to VP2 (the high level of the second operational voltage, such as 23V). Because the node A is high, PMOS transistor M2 is OFF; the voltage VP2 does not affect the voltage level at the output OUT.
When it is desired for the circuit to generate a high voltage level output, as shown at time T1 in FIG. 1B, the input IN switches from low to high, whereby the NMOS transistor M3 turns ON so that the node A is grounded through NMOS transistor M3. However, during the transition state, the PMOS transistor M1 is still partially conductive, and therefore the voltage VP2 still affects the node A; the voltage at the node A does not reach low instantly, but rather drops slowly. The PMOS transistor M2 is controlled by the node A and thus gradually turns ON until time T2. At time T2, the PMOS transistor M2 fully turns ON, and from this time on the voltage VP2 completely passes through the PMOS transistor M2 and reaches the node B so that the output OUT is pulled high to a level equivalent to VP2. In the meantime, since the node B is high, the PMOS transistor M1 fully turns OFF to stabilize node A at the low level of 0V.
As seen from the foregoing description and FIG. 1B, in such a conventional level shift circuit, there is a considerable time delay from the time T1 when the input IN switches to high, till the time T2 when the output OUT reaches high. The time delay is even longer if the level gap between the first and the second operational voltages is considerably large, which is of course undesirable.
In view of the foregoing drawback, the present invention proposes a level shift circuit, which is capable of speeding up the switching time of the PMOS transistors M1 and M2 to thereby speed up output voltage level switching.